1. Field of Invention
The present invention relates to a flash memory array. More particularly, the present invention relates to a split-gate source side injection flash EEPROM array whose floating gates and control gates are fabricated from the same polysilicon layer in the same photolithographic and etching operations.
2. Description of Related Art
A conventional flash memory is a type of electrical erasable programmable read-only memory (EEPROM), which in turn is a type of non-volatile memory. In general, an EEPROM cell comprises two gates. One of the gates known as a floating gate is fabricated from polysilicon and is used for charge storage. The second gate known as the control gate is used for the controlling the input and output of data. The above floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the characteristics of flash memory is its capacity for block-by-block memory erase. Furthermore, the speed of memory erase is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. For most other EEPROM, memory erase can take up to several minutes due to its bit-by-bit operation. Articles concerning flash memory are numerous, and one of them, which produces an improved flash memory structure, is described in U.S. Pat. No. 5,045,488, for example.
FIG. 1 is a cross-sectional view showing the flash memory cell structure according to the U.S. Pat. No. 5,045,488. As shown in FIG. 1, a floating gate 11 and a control gate 12 are formed above a silicon substrate 10. The floating gate 11 and the control gate 12, for example, are polysilicon layers. In between the floating gate 11 and the control gate 12, there is an insulating layer 13. The floating gate 11, the insulating layer 13 and the control gate 12 together constitutes a stacked-gate structure 14. On each sides of the stacked-gate structure 14, ion-doped source and drain regions 15 and 16 are formed in the substrate 10. The characteristic of this type of flash memory cell structure is the split-gate design for the stacked-gate 14. In other words, the floating gate 11 and the control gate 12 are distributed horizontally along the top of the substrate 10. Only a certain central regions of the floating gate 11 and the control gate 12 overlaps such that one is stacked on top of the other in a vertical direction. Furthermore, the floating gate 11 has sharp corners 17 for providing a high electric field, which confers a fast erase capability to the flash memory.
However, in a conventional flash memory, whether the flash memory cell is formed as a two-layered or three-layered polysilicon structure, the ideal gate control gap region formed by the overlapping of two polysilicon layers is difficult to form. For example, as shown in FIG. 1, the gap region near the corners 17 is difficult to create. Moreover, for a multi-layered polysilicon cell, due to a difference in topography, etching is rather difficult and can easily lead to residual stringer structures that result in unwanted short-circuiting between different cells. In addition, because of the existing topographical variation, patterning of the gate region cannot be simultaneously performed in the peripheral circuits and memory cell regions.
Furthermore, in conventional flash memory fabrication, usually a common source terminal is designed for increasing the level of integration and decreasing production cost. Hence, a symmetrical memory cell arrangement, for example, as shown in Fig. 1B, is created generally. Under the highly topographically dependent fabrication techniques, if there is any misalignment of layers, any characteristics that are related to the symmetrical geometry of memory cell pairs will be easily broken through the fabrication. In particular, when the channels 18 and 18' under the control gates 12 and 12' are quite different, data programming efficiency and reading current from the supposedly symmetrical memory cells will become highly unsymmetrical.
In light of the foregoing, there is a need in the art to improve the flash memory array and its method of fabrication.